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HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 64 m b un bu ff ered sdram dim m , 100 mhz m e mor y bus (hb5 2e 88e m ) 8- mwor d 64- bit, 1- bank m odu le ( 8 pcs of 8 m 8 co mp onents ) (hb5 2e 89e m ) 8- mwor d 72- bit, 1- bank m odu le ( 9 pcs of 8 m 8 co mp onents ) 12 8 mb un bu ff ered sd ra m d imm , 10 0 mhz me mo ry bus ( h b52 e1 6 8 e n ) 16 -m wo rd 64- bit, 2- ban k mo dule (1 6 pcs o f 8 m 8 co mpo n ents) ( h b52e 16 9e n) 16 -m wor d 72 -b it, 2- b a nk m o d u l e (1 8 pcs o f 8 m 8 co mpo n ents) pc100 sdram ade-203-1054 ( z) pre limi nary rev. 0.0 apr. 16, 1999 des cri pti o n t he h b 52 e 8 8e m , h b 52 e 89 e m , h b 5 2 e 16 8e n , h b 52 e 1 69 e n be l on g t o 8 - b y t e d i m m ( d u a l i n- l i n e mem o r y mo d u le) f a m ily , an d h a v e b een d e v e lo p e d as an o p t i m i zed m a in m e m o r y so lu tio n f o r 8 - b y te p r o ces- s o r applications . they are s ynch r on ou s dy namic r a m modu l e , mou n ted 6 4 -mb i t s d r a m s (hm5 264 805 f t t) s ealed in tsop packag e, an d 1 piece o f s e rial eepr o m (2-k bit eepr o m) fo r pres ence d e t e c t ( p d ) . t he h b 52 e 8 8e m i s or g a ni z e d 8 m 64 1- bank mou n ted 8 pieces of 6 4 -mb i t s d r a m. the h b 52e8 9em i s org a ni zed 8m 72 1-b a nk mou n ted 9 pieces of 6 4 -mb i t s d r a m. the hb 5 2 e16 8 en i s or g a ni z e d 8 m 64 2- bank m o un ted 16 pieces of 64 -mbit s d r a m. th e hb 52e 1 69 en is o r gan i zed 8m 72 2 - ban k moun ted 18 pieces o f 6 4 -mb i t sdr a m. an ou t lin e of the pr odu c ts is 168 - pin s o ck et type pack - ag e (du a l lead o u t). ther efore, they make h i gh dens ity mo unting po s s ible witho u t s u rface mou n t techn o log y . th ey prov ide commo n d a ta inp u ts and o u tputs . decou p ling capacitor s are m o un ted b e s i d e each tsop on the mo dul e boar d. feature s f u lly c o m p atib le w ith : j e dec st an d a r d o u t lin e u n b u f f e r e d 8 - b y te di mm i n t el p c b r e feren ce des i gn (r ev . 1 .0)
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 2 ? 168-pin socket type package (dual lead out) outline: 133.37 mm (length) 34.925 mm (height) 4.00 mm (thickness) lead pitch: 1.27 mm ? 3.3 v power supply ? clock frequency: 100 mhz (max) ? lvttl interface ? data bus width 64 non parity (HB52E88EM/hb52e168en) 72 ecc (hb52e89em/hb52e169en) ? single pulsed ras ? 4 banks can operates simultaneously and independently ? burst read/write operation and burst read/single write operation capability ? programmable burst length: 1/2/4/8/full page ? 2 variations of burst sequence sequential interleave ? programmable ce latency: 2/3 (HB52E88EM/52e89em/52e168en/52e169en-a6f) : 3 (HB52E88EM/52e89em/52e168en/52e169en-b6f) ? byte control by dqmb ? refresh cycles: 4096 refresh cycles/64 ms ? 2 variations of refresh auto refresh self refresh ? full page burst length capability sequential burst burst stop capability ordering information type no. frequency ce latency package contact pad HB52E88EM-a6f HB52E88EM-b6f 100 mhz 100 mhz 2/3 3 168-pin dual lead out socket type gold hb52e89em-a6f hb52e89em-b6f 100 mhz 100 mhz 2/3 3 hb52e168en-a6f hb52e168en-b6f 100 mhz 100 mhz 2/3 3 hb52e169en-a6f hb52e169en-b6f 100 mhz 100 mhz 2/3 3
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 3 pin arrangement (HB52E88EM/hb52e168en) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 nc 86 dq32 128 cke0 3 dq1 45 s2 87 dq33 129 nc (s3)* 2 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6v cc 48 nc 90 v cc 132 nc 7dq449 v cc 91 dq36 133 v cc 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10dq752nc94dq39136nc 11dq853nc95dq40137nc 12 v ss 54 v ss 96 v ss 138 v ss 13dq955dq1697dq41139dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v cc 101 dq45 143 v cc 18 v cc 60 dq20 102 v cc 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 nc 63 nc (cke1)* 1 105 nc 147 nc 22 nc 64 v ss 106 nc 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 1 pin 10 pin 11 pin 40 pin 41 pin 84 pin 85 pin 94 pin 95 pin 124 pin 125 pin 168 pin
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 4 notes: 1. nc: HB52E88EM, cke1: hb52e168en 2. nc: HB52E88EM, s3: hb52e168en 3. nc: HB52E88EM, s1: hb52e168en (hb52e89em/hb52e169en) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 26 v cc 68 v ss 110 v cc 152 v ss 27 w 69 dq24 111 ce 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 s0 72 dq27 114 nc (s1)* 3 156 dq59 31 nc 73 v cc 115 re 157 v cc 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 ck2 121 a9 163 ck3 38 a10 (ap) 80 nc 122 a13 (ba0) 164 nc 39 a12 (ba1) 81 wp 123 a11 165 sa0 40 v cc 82 sda 124 v cc 166 sa1 41 v cc 83 scl 125 ck1 167 sa2 42 ck0 84 v cc 126 nc 168 v cc pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 nc 86 dq32 128 cke0 3 dq1 45 s2 87 dq33 129 nc (s3)* 2 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6v cc 48 nc 90 v cc 132 nc 7dq449 v cc 91 dq36 133 v cc 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 cb2 94 dq39 136 cb6 11 dq8 53 cb3 95 dq40 137 cb7 12 v ss 54 v ss 96 v ss 138 v ss 13dq955dq1697dq41139dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v cc 101 dq45 143 v cc 18 v cc 60 dq20 102 v cc 144 dq52 19 dq14 61 nc 103 dq46 145 nc
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 5 notes: 1. nc: hb52e89em, cke1: hb52e169en 2. nc: hb52e89em, s3: hb52e169en 3. nc: hb52e89em, s1: hb52e169en pin description (HB52E88EM) 20 dq15 62 nc 104 dq47 146 nc 21 cb0 63 nc (cke1)* 1 105 cb4 147 nc 22 cb1 64 v ss 106 cb5 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 v cc 68 v ss 110 v cc 152 v ss 27 w 69 dq24 111 ce 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 s0 72 dq27 114 nc (s1)* 3 156 dq59 31 nc 73 v cc 115 re 157 v cc 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 ck2 121 a9 163 ck3 38 a10 (ap) 80 nc 122 a13 (ba0) 164 nc 39 a12 (ba1) 81 wp 123 a11 165 sa0 40 v cc 82 sda 124 v cc 166 sa1 41 v cc 83 scl 125 ck1 167 sa2 42 ck0 84 v cc 126 nc 168 v cc pin name function a0 to\~a11 address input row address a0 to a11 column address a0 to a8 a13/a12 bank select address ba0/ba1 dq0 to dq63 data input/output s0, s2 chip select input re row enable (ras) input ce column enable (cas) input w write enable input dqmb0 to dqmb7 byte data mask ck0, ck2 clock input cke0 clock enable input wp write protect for serial pd pin no. pin name pin no. pin name pin no. pin name pin no. pin name
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 6 pin description (hb52e89em) pin description (hb52e168en) sda data input/output for serial pd scl clock input for serial pd sa0 to sa2 serial address input v cc primary positive power supply v ss ground nc no connection pin name function a0 to\~a11 address input row address a0 to a11 column address a0 to a8 a13/a12 bank select address ba0/ba1 dq0 to dq63 data input/output cb0 to cb7 check bit (data input/output) s0, s2 chip select input re row enable (ras) input ce column enable (cas) input w write enable input dqmb0 to dqmb7 byte data mask ck0, ck2 clock input cke0 clock enable input wp write protect for serial pd sda data input/output for serial pd scl clock input for serial pd sa0 to sa2 serial address input v cc primary positive power supply v ss ground nc no connection pin name function a0 to\~a11 address input row address a0 to a11 column address a0 to a8 a13/a12 bank select address ba0/ba1 dq0 to dq63 data input/output s0 to s3 chip select input re row enable (ras) input ce column enable (cas) input w write enable input dqmb0 to dqmb7 byte data mask pin name function
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 7 pin description (hb52e169en) serial pd matrix* 1 ck0 to ck3 clock input cke0, cke1 clock enable input wp write protect for serial pd sda data input/output for serial pd scl clock input for serial pd sa0 to sa2 serial address input v cc primary positive power supply v ss ground nc no connection pin name function a0 to\~a11 address input row address a0 to a11 column address a0 to a8 a13/a12 bank select address ba0/ba1 dq0 to dq63 data input/output cb0 to cb7 check bit (data input/output) s0 to s3 chip select input re row enable (ras) input ce column enable (cas) input w write enable input dqmb0 to dqmb7 byte data mask ck0 to ck3 clock input cke0, cke1 clock enable input wp write protect for serial pd sda data input/output for serial pd scl clock input for serial pd sa0 to sa2 serial address input v cc primary positive power supply v ss ground nc no connection byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 0 number of bytes used by module manufacturer 1000000080 128 1 total spd memory size 0000100008 256 byte 2 memory type 0000010004 sdram 3 number of row addresses bits 000011000c 12 pin name function
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 8 4 number of column addresses bits 0000100109 9 5 number of banks (HB52E88EM/89em) 0000000101 1 (hb52e168en/169en) 0000001002 2 6 module data width (HB52E88EM/168en) 0100000040 64 (hb52e89em/169en) 0100100048 72 7 module data width (continued) 0000000000 0 (+) 8 module interface signal levels0000000101 lvttl 9 sdram cycle time (highest ce latency) 10 ns 10100000a0 cl = 3 10 sdram access from clock (highest ce latency) 6 ns 0110000060 11 module configuration type (HB52E88EM/168en) 0000000000 non parity (hb52e89em/169en) 0000001002 ecc 12refresh rate/type 1000000080 normal (15.625 m s) self refresh 13sdram width 0000100008 8m 8 14 error checking sdram width (HB52E88EM/168en) 0000000000 (hb52e89em/169en) 0000100008 8 15 sdram device attributes: minimum clock delay for back-to-back random column addresses 0000000101 1 clk 16 sdram device attributes: burst lengths supported 100011118f 1, 2, 4, 8, full page 17 sdram device attributes: number of banks on sdram device 0000010004 4 18 sdram device attributes: ce latency (-a6f) 0000011006 2, 3 sdram device attributes: ce latency (-b6f) 0000010004 3 19 sdram device attributes: s latency 0000000101 0 20 sdram device attributes: w latency 0000000101 0 21sdram module attributes0000000000 non buffer 22 sdram device attributes: general 000011100e v cc 10% byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 9 23 sdram cycle time (2nd highest ce latency) (-a6f) 10 ns 10100000a0 cl = 2 sdram cycle time (2nd highest ce latency) (-b6f) undefined 0000000000 24 sdram access from clock (2nd highest ce latency) (-a6f) 6 ns 0110000060 cl = 2 sdram access from clock (2nd highest ce latency) (-b6f) undefined 0000000000 25 sdram cycle time (3rd highest ce latency) undefined 0000000000 26 sdram access from clock (3rd highest ce latency) undefined 0000000000 27minimum row precharge time0001010014 20 ns 28row active to row active min0001010014 20 ns 29re to ce delay min 0001010014 20 ns 30minimum re pulse width 0011001032 50 ns 31 density of each bank on module (HB52E88EM/89em) 0001000010 1 bank 64 m byte (hb52e168en/169en) 0001000010 2 bank 64 m byte 32 address and command signal input setup time 0010000020 2.0 ns 33 address and command signal input hold time 0001000010 1.0 ns 34data signal input setup time0010000020 2.0 ns 35data signal input hold time0001000010 1.0 ns 36 to 61 superset information 0000000000 future use 62spd data revision code 0001001012 rev.1.2a 63 checksum for bytes 0 to 62 (HB52E88EM-a6f) 0000010105 5 (HB52E88EM-b6f) 0000001103 3 (hb52e89em-a6f) 0001011117 23 (hb52e89em-b6f) 0001010115 21 (hb52e168en-a6f) 0000011006 6 (hb52e168en-b6f) 0000010004 4 (hb52e169en-a6f) 0001100018 24 (hb52e169en-b6f) 0001011016 22 64 manufacturers jedec id code 0000011107 hitachi byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 10 notes: 1. all serial pd data are not protected. 0: serial data, driven low, 1: serial data, driven high these spd are based on intel specification (rev.1.2a). 2. regarding byte32 to 35, based on jedec committee ballot jc42.5-97-119. 3. byte72 is manufacturing location code. (ex: in case of japan, byte72 is 4ah. 4ah shows j on ascii code.) 65 to 71 manufacturers jedec id code 0000000000 72 manufacturing location * 3 (ascii-8bit code) 73manufacturers part number0100100048 h 74manufacturers part number0100001042 b 75manufacturers part number0011010135 5 76manufacturers part number0011001032 2 77manufacturers part number0100010145 e 78 manufacturers part number (HB52E88EM/89em) 0011100038 8 (hb52e168en/169en) 0011000131 1 79 manufacturers part number (HB52E88EM) 0011100038 8 (hb52e89em) 0011100139 9 (hb52e168en/169en) 0011011036 6 80 manufacturers part number (HB52E88EM/89em) 0100010145 e (hb52e168en) 0011100038 8 (hb52e169en) 0011100139 9 81 manufacturers part number (HB52E88EM/89em) 010011014d m (hb52e168en/169en) 0100010145 e 82 manufacturers part number (HB52E88EM/89em) 001011012d (hb52e168en/169en) 010011104e n 83 manufacturers part number (HB52E88EM/89em-a6f)0100000141 a (HB52E88EM/89em-b6f)0100001042 b (hb52e168en/169en) 001011012d 84 manufacturers part number (HB52E88EM/89em) 0011011036 6 (hb52e168en/169en- a6f) 0100000141 a (hb52e168en/169en- b6f) 0100001042 b 85 manufacturers part number (HB52E88EM/89em) 0100011046 f (hb52e168en/169en) 0011011036 6 86 manufacturers part number (HB52E88EM/89em) 0010000020 (space) byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 11 4. regarding byte93 and 94, based on jedec committee ballot jc42.5-97-135. bcd is binary coded decimal. 5. all bits of 99 through 125 are not defined (1 or 0). 6. bytes 95 through 98 are assembly serial number. block diagram (HB52E88EM) dqmb0 d1 i/o0 to i/o7 i/o0 to i/o7 dqm dqm dq0 to dq7 dq8 to dq15 dqmb1 * d0 to d7: hm5264805 u0: 2-kbit eeprom c0 to c7: 0.33 f c8 to c15: 0.10 f c100, c101: 10 pf n0 to n17: network registor 10 w r100 to r103: 10 w r1: 47 k w v cc (d0 to d7, u0) v ss (d0 to d7, u0) serial pd sda wp r1 v ss a0 a1 a2 sa0 sa1 sa2 v ss v cc scl u0 sda scl notes : 1. the sda pull-up resistor is required due to the open-drain/open-collector output. 2. the scl pull-up resistor is recommended because of the normal scl line inacitve r100 r101 ck0 ck1, ck3 clk :4 sdrams + 3.3 pf cap clk :4 sdrams + 3.3 pf cap 8 n0, n1 8 n2, n3 dqmb4 dq32 to dq39 dq40 to dq47 dqmb5 8 n8, n9 8 n10, n11 cke0 cke (d0 to d7) ck2 r102, r103 c100, c101 c8 to c15 c0 to c7 re , ce , w cs cs d5 d4 d0 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs s0 s2 "high" state. dqmb2 d3 i/o0 to i/o7 i/o0 to i/o7 dqm dqm dq16 to dq23 dq24 to dq31 dqmb3 8 n4, n5 8 n6, n7 dqmb6 dq48 to dq55 dq56 to dq63 dqmb7 8 n12, n13 8 n14, n15 cs cs d7 d6 d2 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs a0 to a13
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 12 block diagram (hb52e89em) dqmb0 d1 i/o0 to i/o7 i/o0 to i/o7 dqm dqm dq0 to dq7 dq8 to dq15 dqmb1 * d0 to d8: hm5264805 u0: 2-kbit eeprom c0 to c9: 0.33 f, c10 to c19: 0.10 f c100, c101: 10 pf r1: 47 k w n0 to n17: network registor 10 w r100 to r103: 10 w v cc (d0 to d8, u0) v ss (d0 to d8, u0) serial pd sda wp r1 a0 a1 a2 sa0 sa1 sa2 v ss v ss v cc scl u0 sda scl notes: 1. the sda pull-up resistor is required due to the open-drain/open-collector output. 2. the scl pull-up resistor is recommended because of the normal scl line inacitve 8 n0, n1 8 n2, n3 dqmb4 dq32 to dq39 dq40 to dq47 dqmb5 8 n10, n11 8 n12, n13 c9 to c17 c0 to c8 re , ce , w cs cs d2 i/o0 to i/o7 dqm cb0 to cb7 8 n4, n5 cs d6 d5 d0 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs s0 s2 "high" state. dqmb2 d4 i/o0 to i/o7 i/o0 to i/o7 dqm dqm dq16 to dq23 dq24 to dq31 dqmb3 8 n6, n7 8 n8, n9 dqmb6 dq48 to dq55 dq56 to dq63 dqmb7 8 n14, n15 8 n16, n17 cs cs d8 d7 d3 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs a0 to a13 r100 ck0 clk ; 5 sdrams r102 ck2 clk; 4 sdrams + 3.3 pf cap cke (d0 to d8) cke0 ck1 r101 c100 ck3 r103 c101
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 13 block diagram (hb52e168en) dqmb0 d1 i/o0 to i/o7 i/o0 to i/o7 dqm dqm dq0 to dq7 dq8 to dq15 dqmb1 * d0 to d15: hm5264805 u0: 2-kbit eeprom c0 to c15: 0.33 f, c16 to c31: 0.10 f r0: 10 k w , r1: 47 k w n0 to n15: network registor 10 w r100 to r103: 10 w cke (d8 to d15) serial pd sda wp r1 a0 a1 a2 sa0 sa1 sa2 v ss cke1 cke (d0 to d7) cke0 scl u0 sda scl notes : 1. the sda pull-up resistor is required due to the open-drain/open-collector output. 2. the scl pull-up resistor is recommended because of the normal scl line inacitve r0 8 n0, n1 n2, n3 n4, n5 n6, n7 n8, n9 n10, n11 n12, n13 n14, n15 8 dqmb4 dq32 to dq39 dq40 to dq47 dqmb5 8 8 v cc (d0 to d15, u0) v ss (d0 to d15, u0) v ss v cc v cc c16 to c31 c0 to c15 re , ce , w cs cs d5 d4 d0 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs s1 s2 "high" state. dqmb2 d3 i/o0 to i/o7 i/o0 to i/o7 dqm dqm dq16 to dq23 dq24 to dq31 dqmb3 8 8 dqmb6 dq48 to dq55 dq56 to dq63 dqmb7 8 8 cs cs d7 d6 d2 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs s0 a0 to a13 d13 d12 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs s3 d15 d14 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs d9 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs d8 d11 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs d10 r100 r101 ck0 clk; 4 sdrams + 3.3 pf cap clk; 4 sdrams + 3.3 pf cap ck1 r102 r103 ck2 clk; 4 sdrams + 3.3 pf cap clk; 4 sdrams + 3.3 pf cap ck3
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 14 block diagram (hb52e169en) dqmb0 d1 i/o0 to i/o7 i/o0 to i/o7 dqm dqm dq0 to dq7 dq8 to dq15 dqmb1 * d0 to d17: hm5264805 u0: 2-kbit eeprom c0 to c17: 0.33 f, c18 to c35: 0.10 f r0: 10 k w , r1: 47 k w n0 to n17: network registor 10 w r100 to r103: 10 w cke (d9 to d17) serial pd sda a0 a1 a2 sa0 sa1 sa2 v cc cke1 cke (d0 to d8) cke0 scl u0 sda scl notes : 1. the sda pull-up resistor is required due to the open-drain/open-collector output. 2. the scl pull-up resistor is recommended 3. sdram d11 dqmb input is wired to dqmb5 because of the normal scl line inacitve r0 8 n0, n1 n4, n5 n6, n7 n8, n9 n10, n11 n12, n13 n14, n15 n16, n17 8 dqmb4 dq32 to dq39 dq40 to dq47 dqmb5 8 8 v cc (d0 to d17, u0) v ss (d0 to d17, u0) v ss v cc c18 to c35 c0 to c17 v ss r1 re , ce , w cs cs d6 d5 d0 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs s1 s2 "high" state. dqmb2 d4 i/o0 to i/o7 i/o0 to i/o7 dqm dqm dq16 to dq23 dq24 to dq31 dqmb3 8 8 dqmb6 dq48 to dq55 dq56 to dq63 dqmb7 8 8 cs cs d8 d7 d3 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs s0 a0 to a13 d15 d14 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs s3 d17 d16 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs d10 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs d2 i/o0 to i/o7 dqm cb0 to cb7 8 cs d11 i/o0 to i/o7 dqm cs d9 d13 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs d12 r100 r101 ck0 clk (5 sdrams) clk (5 sdrams) ck1 r102 r103 ck2 clk (4 sdrams + 3.3 pf cap) clk (4 sdrams + 3.3 pf cap) ck3 wp n2, n3
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 15 absolute maximum ratings note: 1. respect to v ss dc operating conditions (ta = 0 to +65 c) notes: 1. all voltage referred to v ss 2. the supply voltage with all vcc pins must be on the same level. 3. the supply voltage with all vss pins must be on the same level. 4. ck, cke, s, dqmb, dq pins: v ih (max) = v cc + 0.5 v for pulse width 5 ns at v cc . 5. others: v ih (max) = 4.6 v for pulse width 5 ns at v cc . 6. v il (min) = C1.0 v for pulse width 5 ns at v ss . v il /v ih clamp (component characteristic) this sdram component has v il and v ih clamp for ck, cke, s , dqmb and dq pins. minimum v il clamp current parameter symbol value unit note voltage on any pin relative to v ss v t C0.5 to v cc + 0.5 ( 4.6 (max)) v1 supply voltage relative to v ss v cc C0.5 to +4.6 v 1 short circuit output current iout 50 ma power dissipation (HB52E88EM/ 168en) p t 8.0 w power dissipation (hb52e89em/ 169en) p t 9.0 w operating temperature topr 0 to +65 c storage temperature tstg C55 to +125 c parameter symbol min max unit notes supply voltage v cc 3.0 3.6 v 1, 2 v ss 00v3 input high voltage v ih 2.0 v cc + 0.3 v 1, 4, 5 input low voltage v il C0.3 0.8 v 1, 6 v il (v) i (ma) C2 C32 C1.8 C25 C1.6 C19 C1.4 C13 C1.2 C8 C1 C4 C0.9 C2 C0.8 C0.6 C0.6 0
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 16 minimum v ih clamp current C0.4 0 C0.2 0 00 v ih (v) i (ma) v cc + 2 10 v cc + 1.8 8 v cc + 1.6 5.5 v cc + 1.4 3.5 v cc + 1.2 1.5 v cc + 1 0.3 v cc + 0.8 0 v cc + 0.6 0 v cc + 0.4 0 v cc + 0.2 0 v cc + 0 0 v il (v) i (ma) v il (v) i (ma) e1.5 e1 e0.5 e5 e15 e10 e25 e20 e30 0 e35 e2 0 v ih (v) v cc + 0 v cc + 1 v cc + 2 v cc + 0.5 v cc + 1.5 i (ma) 8 4 6 0 2 10
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 17 i ol /i oh characteristics (component characteristic) output low current (i ol ) output high current (i oh ) (ta = 0 to 65 c, v cc = 3.0 v to 3.45 v, v ss = 0 v) i ol i ol vout (v) min (ma) max (ma) 00 0 0.4 27 71 0.65 41 108 0.85 51 134 158 151 1.4 70 188 1.5 72 194 1.65 75 203 1.8 77 209 1.95 77 212 380 220 3.45 81 223 i oh i oh vout (v) min (ma) max (ma) 3.45 C3 3.3 C28 30 C75 2.6 C21 C130 i ol (ma) vout (v) 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 min max
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 18 dc characteristics (ta = 0 to 65 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (HB52E88EM) 2.4 C34 C154 2 C59 C197 1.8 C67 C227 1.65 C73 C248 1.5 C78 C270 1.4 C81 C285 1 C89 C345 0 C93 C503 parameter symbol HB52E88EM unit test conditions notes -a6f/b6f min max operating current (ce latency = 2) i cc1 560ma burst length = 1 t rc = min 1, 2, 3 (ce latency = 3) i cc1 560ma standby current in power down i cc2p 24 ma cke = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 16 ma cke = v il , t ck = 7 standby current in non power down i cc2n 128 ma cke, s = v ih , t ck = 12 ns 4 active standby current in power down i cc3p 32 ma cke = v il , t ck = 12 ns 1, 2, 6 i oh i oh vout (v) min (ma) max (ma) i oh (ma) vout (v) 0 e100 e200 e300 e500 e600 e400 0.5 1 1.5 2 2.5 3 min max 3.5 0
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 19 notes: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are changed once per four clocks. 6. after power down mode, ck operating current. 7. after power down mode, no ck operating current. 8. after self refresh mode set, self refresh current. dc characteristics (ta = 0 to 65 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hb52e89em) active standby current in non power down i cc3n 160 ma cke, s = v ih , t ck = 12 ns 1, 2, 4 burst operating current (ce latency = 2) i cc4 640ma t ck = min, bl = 4 1, 2, 5 (ce latency = 3) i cc4 640ma refresh current i cc5 920mat rc = min 3 self refresh current i cc6 8 mav ih 3 v cc C 0.2 v v il 0.2 v 8 input leakage current i li C10 10 m a0 vin v cc output leakage current i lo C10 10 m a0 vout v cc dq = disable output high voltage v oh 2.4 v i oh = C4 ma output low voltage v ol 0.4vi ol = 4 ma parameter symbol hb52e89em unit test conditions notes -a6f/b6f min max operating current (ce latency = 2) i cc1 630ma burst length = 1 t rc = min 1, 2, 3 (ce latency = 3) i cc1 630ma standby current in power down i cc2p 27 ma cke = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 18 ma cke = v il , t ck = 7 standby current in non power down i cc2n 144 ma cke, s = v ih , t ck = 12 ns 4 active standby current in power down i cc3p 36 ma cke = v il , t ck = 12 ns 1, 2, 6 active standby current in non power down i cc3n 180 ma cke, s = v ih , t ck = 12 ns 1, 2, 4 burst operating current (ce latency = 2) i cc4 720ma t ck = min, bl = 4 1, 2, 5 (ce latency = 3) i cc4 720ma parameter symbol HB52E88EM unit test conditions notes -a6f/b6f min max
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 20 notes: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are changed once per four clocks. 6. after power down mode, ck operating current. 7. after power down mode, no ck operating current. 8. after self refresh mode set, self refresh current. dc characteristics (ta = 0 to 65 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hb52e168en) refresh current i cc5 1035 ma t rc = min 3 self refresh current i cc6 9 mav ih 3 v cc C 0.2 v v il 0.2 v 8 input leakage current i li C10 10 m a0 vin v cc output leakage current i lo C10 10 m a0 vout v cc dq = disable output high voltage v oh 2.4 v i oh = C4 ma output low voltage v ol 0.4vi ol = 4 ma parameter symbol hb52e168en unit test conditions notes -a6f/b6f min max operating current (ce latency = 2) i cc1 720ma burst length = 1 t rc = min 1, 2, 3 (ce latency = 3) i cc1 720ma standby current in power down i cc2p 48 ma cke = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 32 ma cke = v il , t ck = 7 standby current in non power down i cc2n 256 ma cke, s = v ih , t ck = 12 ns 4 active standby current in power down i cc3p 64 ma cke = v il , t ck = 12 ns 1, 2, 6 active standby current in non power down i cc3n 320 ma cke, s = v ih , t ck = 12 ns 1, 2, 4 burst operating current (ce latency = 2) i cc4 800ma t ck = min, bl = 4 1, 2, 5 (ce latency = 3) i cc4 800ma refresh current i cc5 1080 ma t rc = min 3 self refresh current i cc6 16mav ih 3 v cc C 0.2 v v il 0.2 v 8 input leakage current i li C10 10 m a0 vin v cc parameter symbol hb52e89em unit test conditions notes -a6f/b6f min max
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 21 notes: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are changed once per four clocks. 6. after power down mode, ck operating current. 7. after power down mode, no ck operating current. 8. after self refresh mode set, self refresh current. dc characteristics (ta = 0 to 65 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hb52e169en) output leakage current i lo C10 10 m a0 vout v cc dq = disable output high voltage v oh 2.4 v i oh = C4 ma output low voltage v ol 0.4vi ol = 4 ma parameter symbol hb52e169en unit test conditions notes -a6f/b6f min max operating current (ce latency = 2) i cc1 810ma burst length = 1 t rc = min 1, 2, 3 (ce latency = 3) i cc1 810ma standby current in power down i cc2p 54 ma cke = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 36 ma cke = v il , t ck = 7 standby current in non power down i cc2n 288 ma cke, s = v ih , t ck = 12 ns 4 active standby current in power down i cc3p 72 ma cke = v il , t ck = 12 ns 1, 2, 6 active standby current in non power down i cc3n 360 ma cke, s = v ih , t ck = 12 ns 1, 2, 4 burst operating current (ce latency = 2) i cc4 900ma t ck = min, bl = 4 1, 2, 5 (ce latency = 3) i cc4 900ma refresh current i cc5 1215 ma t rc = min 3 self refresh current i cc6 18mav ih 3 v cc C 0.2 v v il 0.2 v 8 input leakage current i li C10 10 m a0 vin v cc output leakage current i lo C10 10 m a0 vout v cc dq = disable output high voltage v oh 2.4 v i oh = C4 ma output low voltage v ol 0.4vi ol = 4 ma parameter symbol hb52e168en unit test conditions notes -a6f/b6f min max
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 22 notes: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are changed once per four clocks. 6. after power down mode, ck operating current. 7. after power down mode, no ck operating current. 8. after self refresh mode set, self refresh current. capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) (HB52E88EM) notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. measurement condition: f = 1 mhz, 1.4 v bias, 200 mv swing. 3. dqmb = v ih to disable data-out. 4. this parameter is sampled and not 100% tested. capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) (hb52e89em) notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. measurement condition: f = 1 mhz, 1.4 v bias, 200 mv swing. 3. dqmb = v ih to disable data-out. 4. this parameter is sampled and not 100% tested. parameter symbol max unit notes input capacitance (address) c i1 70 pf 1, 2, 4 input capacitance (re, ce, w) c i2 63 pf 1, 2, 4 input capacitance (cke) c i3 68 pf 1, 2, 4 input capacitance (s) c i4 34 pf 1, 2, 4 input capacitance (ck) c i5 50 pf 1, 2, 4 input capacitance (dqmb) c i6 16 pf 1, 2, 4 input/output capacitance (dq) c i/o1 14 pf 1, 2, 3, 4 parameter symbol max unit notes input capacitance (re, ce, w) c i2 66 pf 1, 2, 4 input capacitance (cke) c i3 70 pf 1, 2, 4 input capacitance (s) c i4 39 pf 1, 2, 4 input capacitance (ck) c i5 50 pf 1, 2, 4 input capacitance (dqmb) c i6 21 pf 1, 2, 4 input/output capacitance (dq) c i/o1 14 pf 1, 2, 3, 4
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 23 capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) (hb52e168en) notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. measurement condition: f = 1 mhz, 1.4 v bias, 200 mv swing. 3. dqmb = v ih to disable data-out. 4. this parameter is sampled and not 100% tested. capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) (hb52e169en) notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. measurement condition: f = 1 mhz, 1.4 v bias, 200 mv swing. 3. dqmb = v ih to disable data-out. 4. this parameter is sampled and not 100% tested. ac characteristics (ta = 0 to 65 c, v cc = 3.3 v 0.3 v, v ss = 0 v) parameter symbol max unit notes input capacitance (address) c i1 105 pf 1, 2, 4 input capacitance (re, ce, w) c i2 90 pf 1, 2, 4 input capacitance (cke) c i3 68 pf 1, 2, 4 input capacitance (s) c i4 38 pf 1, 2, 4 input capacitance (ck) c i5 50 pf 1, 2, 4 input capacitance (dqmb) c i6 23 pf 1, 2, 4 input/output capacitance (dq) c i/o1 22 pf 1, 2, 3, 4 parameter symbol max unit notes input capacitance (address) c i1 112 pf 1, 2, 4 input capacitance (re, ce, w) c i2 97 pf 1, 2, 4 input capacitance (cke) c i3 70 pf 1, 2, 4 input capacitance (s) c i4 40 pf 1, 2, 4 input capacitance (ck) c i5 50 pf 1, 2, 4 input capacitance (dqmb) c i6 27 pf 1, 2, 4 input/output capacitance (dq) c i/o1 22 pf 1, 2, 3, 4 parameter hitachi- symbol pc100 symbol HB52E88EM/89em/ 168en/169en unit notes -a6f/b6f min max system clock cycle time (ce latency = 2) t ck tclk 10 ns 1 (ce latency = 3) t ck tclk 10 ns ck high pulse width t ckh tch 3 ns 1 ck low pulse width t ckl tcl 3 ns 1 access time from ck (ce latency = 2) t ac tac 6 ns 1, 2 (ce latency = 3) t ac tac 6 ns data-out hold time t oh toh 3 ns 1, 2
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 24 notes: 1. ac measurement assumes t t = 1 ns. reference level for timing of input signals is 1.5 v. 2. access time is measured at 1.5 v. load condition is c l = 50 pf. 3. t lz (max) defines the time at which the outputs achieves the low impedance state. 4. t hz (max) defines the time at which the outputs achieves the high impedance state. 5. t ces defines cke setup time to ck rising edge except power down exit command. test conditions ? input and output timing reference levels: 1.5 v ? input waveform and output load: see following figures ck to data-out low impedance t lz 2 ns 1, 2, 3 ck to data-out high impedance t hz 6 ns 1, 4 data-in setup time t ds tsi 2 ns 1 data in hold time t dh thi 1 ns 1 address setup time t as tsi 2 ns 1 address hold time t ah thi 1 ns 1 cke setup time t ces tsi 2 ns 1, 5 cke setup time for power down exit t cesp tpde 2 ns 1 cke hold time t ceh thi 1 ns 1 command setup time t cs tsi 2 ns 1 command hold time t ch thi 1 ns 1 ref/active to ref/active command period t rc trc 70 ns 1 active to precharge command period t ras tras 50 120000 ns 1 active command to column command (same bank) t rcd trcd 20 ns 1 precharge to active command period t rp trp 20 ns 1 write recovery or data-in to precharge lead time t dpl tdpl 15 ns 1 active (a) to active (b) command period t rrd trrd 20 ns 1 transition time (rise to fall) t t 15ns refresh period t ref 64ms parameter hitachi- symbol pc100 symbol HB52E88EM/89em/ 168en/169en unit notes -a6f/b6f min max t t 2.4 v 0.4 v 0.8 v 2.0 v input t t dq cl
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 25 relationship between frequency and minimum latency notes: 1. i rcd to i rrd are recommended value. parameter hitachi- symbol pc100 symbol HB52E88EM/ 89em/ 168en/169en notes -a6f/b6f frequency (mhz) 100 t ck (ns) 10 active command to column command (same bank) i rcd 21 active command to active command (same bank) i rc 7 = [i ras + i rp ] 1 active command to precharge command (same bank) i ras 51 precharge command to active command (same bank) i rp 21 write recovery or data-in to precharge command (same bank) i dpl tdpl 2 1 active command to active command (different bank) i rrd 21 self refresh exit time i srex tsrx 1 2 last data in to active command (auto precharge, same bank) i apw tdal 4 = [i dpl + i rp ] self refresh exit to command input i sec 7 = [i rc ] 3 precharge command to high impedance (ce latency = 2) i hzp troh 2 (ce latency = 3) i hzp troh 3 last data out to active command (auto precharge) (same bank) i apr 1 last data out to precharge (early precharge) (ce latency = 2) i ep C1 (ce latency = 3) i ep C2 column command to column command i ccd tccd 1 write command to data in latency i wcd tdwd 0 dqmb to data in i did tdqm 0 dqmb to data out i dod tdqz 2 cke to ck disable i cle tcke 1 register set to active command i rsa tmrd 1 s to command disable i cdd 0 power down exit to command input i pec 1 burst stop to output valid data hold (ce latency = 2) i bsr 1 (ce latency = 3) i bsr 2 burst stop to output high impedance (ce latency = 2) i bsh 2 (ce latency = 3) i bsh 3 burst stop to write data ignore i bsw 0
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 26 2. be valid [dsel] or [nop] at next command of self refresh exit. 3. except [dsel] and [nop] pin functions ck0 to ck3 (input pin): ck is the master clock input to this pin. the other input signals are referred at ck rising edge. s0 to s3 (input pin): when s is low, the command input cycle becomes valid. when s is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. re , ce and w (input pins): although these pin names are the same as those of conventional drams, they function in a different way. these pins define operation commands (read, write, etc.) depending on the com- bination of their voltage levels. for details, refer to the command operation section. a0 to a11 (input pins): row address (ax0 to ax11) is determined by a0 to a11 level at the bank active command cycle ck rising edge. column address (ay0 to ay8) is determined by a0 to a8 level at the read or write command cycle ck rising edge. and this column address becomes burst access start address. a10 defines the precharge mode. when a10 = high at the precharge command cycle, all banks are precharged. but when a10 = low at the precharge command cycle, only the bank that is selected by a12/a13 (ba) is precharged. a12/a13 (input pin): a12/a13 are bank select signal (ba). the memory array is divided into bank 0, bank 1, bank 2 and bank 3. if a12 is low and a13 is low, bank 0 is selected. if a12 is high and a13 is low, bank 1 is selected. if a12 is low and a13 is high, bank 2 is selected. if a12 is high and a13 is high, bank 3 is selected. cke0, cke1 (input pin): this pin determines whether or not the next ck is valid. if cke is high, the next ck rising edge is valid. if cke is low, the next ck rising edge is invalid. this pin is used for power- down and clock suspend modes. dqmb0 to dqmb7 (input pins): read operation: if dqmb is high, the output buffer becomes high-z. if the dqmb is low, the output buffer becomes low-z. write operation: if dqmb is high, the previous data is held (the new data is not written). if dqmb is low, the data is written. dq0 to dq63 (input/output pins): data is input to and output from these pins. cb0 to cb7 (input/output pins): data is input to and output from these pins. v cc (power supply pins): 3.3 v is applied. v ss (power supply pins): ground is connected. command operation command truth table the sdram module recognizes the following commands specified by the s , re , ce , w and address pins.
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 27 note: h: v ih . l: v il . : v ih or v il . v: valid address input ignore command [desl]: when this command is set (s is high), the sdram module ignore command input at the clock. however, the internal status is held. no operation [nop]: this command is not an execution command. however, the internal operations con- tinue. burst stop in full-page [bst]: this command stops a full-page burst operation (burst length = full-page) and is illegal otherwise. when data input/output is completed for a full page of data, it automatically returns to the start address, and input/output is performed repeatedly. column address strobe and read command [read]: this command starts a read operation. in addition, the start address of burst read is determined by the column address and the bank select address (ba). after the read operation, the output buffer becomes high-z. read with auto-precharge [read a]: this command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8. when the burst length is full-page, this command is illegal. column address strobe and write command [writ]: this command starts a write operation. when the burst write mode is selected, the column address and the bank select address (ba) become the burst write start address. when the single write mode is selected, data is only written to the location specified by the column address and the bank select address (ba). write with auto-precharge [writ a]: this command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. when the burst length is full-page, this command is illegal. row address strobe and bank activate [actv]: this command activates the bank that is selected by bank select address (ba) and determines the row address (ax0 to ax11). when a12 and a13 are low, bank 0 is activated. when a12 is high and a13 is low, bank 1 is activated. when a12 is low and a13 is high, bank 2 is activated. when a12 and a13 are high, bank 3 is activated. precharge selected bank [pre]: this command starts precharge operation for the bank selected by a12/ a13. if a12 and a13 are low, bank 0 is selected. if a12 is high and a13 is low, bank 1 is selected. if a12 is low and a13 is high, bank 2 is selected. if a12 and a13 are high, bank 3 is selected. command symbol cke a12/ a13 a10 a0 to a11 n - 1n s recew ignore command desl h h no operation nop h l hhh burst stop in full page bst h l hhl column address and read command read h lhlhv lv read with auto-precharge read a h lhlhv hv column address and write command writ h lhllv lv write with auto-precharge writ a h lhllv hv row address strobe and bank active actv h l l hhv vv precharge select bank pre h llhlv l precharge all bank pall h llhl h refresh ref/selfh vlllh mode register set mrs h llllv vv
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 28 precharge all banks [pall]: this command starts a precharge operation for all banks. refresh [ref/self]: this command starts the refresh operation. there are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. for details, refer to the cke truth table section. mode register set [mrs]: the sdram module has a mode register that defines how it operates. the mode register is specified by the address pins (a0 to a13) at the mode register set cycle. for details, refer to the mode register configuration. after power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. dqmb truth table note: h: v ih . m l: v il . : v ih or v il . write: i did is needed. read: i dod is needed. the sdram module can mask input/output data by means of dqmb. during reading, the output buffer is set to low-z by setting dqmb to low, enabling data output. on the other hand, when dqmb is set to high, the output buffer becomes high-z, disabling data output. during writing, data is written by setting dqmb to low. when dqmb is set to high, the previous data is held (the new data is not written). desired data can be masked during burst read or burst write by setting dqmb. for details, refer to the dqmb control section of the sdram module operating instructions. cke truth table note: h: v ih . l: v il . : v ih or v il . clock suspend mode entry: the sdram module enters clock suspend mode from active mode by setting cke to low. the clock suspend mode changes depending on the current status (1 clock before) as shown below. command symbol cke dqmb n - 1 n write enable/output enable enb h l write inhibit/output disable mask h h current state command cke s re ce w address n - 1 n active clock suspend mode entry h l h any clock suspend l l clock suspend clock suspend mode exit l h idle auto-refresh command (ref) h h l l l h idle self-refresh entry (self) h l l l l h idle power down entry h l l h h h hl h self refresh self refresh exit (selfx) l h l h h h lhh power down power down exit l h l h h h lhh
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 29 active clock suspend: this suspend mode ignores inputs after the next clock by internally maintaining the bank active status. read suspend and read with auto-precharge suspend: the data being output is held (and continues to be output). write suspend and writ with auto-precharge suspend: in this mode, external signals are not accept- ed. however, the internal state is held. clock suspend: during clock suspend mode, keep the cke to low. clock suspend mode exit: the sdram module exits from clock suspend mode by setting cke to high during the clock suspend state. idle: in this state, all banks are not selected, and completed precharge operation. auto-refresh command [ref]: when this command is input from the idle state, the sdram module starts auto-refresh operation. (the auto-refresh is the same as the cbr refresh of conventional drams.) during the auto-refresh operation, refresh address and bank select address are generated inside the sdram module. for every auto-refresh cycle, the internal address counter is updated. accordingly, 4096 times are required to refresh the entire memory. before executing the auto-refresh command, all the banks must be in the idle state. in addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge command is required after auto-refresh. self-refresh entry [self]: when this command is input during the idle state, the sdram module starts self-refresh operation. after the execution of this command, self-refresh continues while cke is low. since self-refresh is performed internally and automatically, external refresh operations are unnecessary. power down mode entry: when this command is executed during the idle state, the sdram module en- ters power down mode. in power down mode, power consumption is suppressed by cutting off the initial in- put circuit. self-refresh exit: when this command is executed during self-refresh mode, the sdram module can exit from self-refresh mode. after exiting from self-refresh mode, the sdram module enters the idle state. power down exit: when this command is executed at the power down mode, the sdram module can exit from power down mode. after exiting from power down mode, the sdram module enters the idle state. function truth table the following table shows the operations that are performed when each command is issued in each mode of the sdram module. the following table assumes that cke is high. current state s re ce w address command operation precharge h desl enter idle after t rp lhhh nop enter idle after t rp lhhl bst nop l h l h ba, ca, a10 read/read a illegal* 4 l h l l ba, ca, a10 writ/writ a illegal* 4 l l h h ba, ra actv illegal* 4 l l h l ba, a10 pre, pall nop* 6 lllh ref, self illegal llllmode mrs illegal
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 30 idle h desl nop lhhh nop nop lhhl bst nop l h l h ba, ca, a10 read/read a illegal* 5 l h l l ba, ca, a10 writ/writ a illegal* 5 l l h h ba, ra actv bank and row active l l h l ba, a10 pre, pall nop lllh ref, self refresh l l l l mode mrs mode register set row active h desl nop lhhh nop nop lhhl bst nop l h l h ba, ca, a10 read/read a begin read l h l l ba, ca, a10 writ/writ a begin write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall precharge lllh ref, self illegal llllmode mrs illegal read h desl continue burst to end lhhh nop continue burst to end lhhl bst burst stop to full page l h l h ba, ca, a10 read/read a continue burst read to ce latency and new read l h l l ba, ca, a10 writ/writ a term burst read/start write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall term burst read and precharge lllh ref, self illegal llllmode mrs illegal read with auto- precharge h desl continue burst to end and precharge lhhh nop continue burst to end and precharge lhhl bst illegal l h l h ba, ca, a10 read/read a illegal* 4 l h l l ba, ca, a10 writ/writ a illegal* 4 l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall illegal* 4 lllh ref, self illegal llllmode mrs illegal current state s re ce w address command operation
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 31 notes: 1. h: v ih . l: v il . : v ih or v il . the other combinations are inhibit. 2. an interval of t dpl is required between the final valid data input and the precharge command. 3. if t rrd is not satisfied, this operation is illegal. 4. illegal for same bank, except for another bank. 5. illegal for all banks. 6. nop for same bank, except for another bank. from precharge state, command operation to [desl], [nop] or [bst]: when these commands are executed, the sdram module enters the idle state after t rp has elapsed from the completion of precharge. write h desl continue burst to end lhhh nop continue burst to end lhhl bst burst stop on full page l h l h ba, ca, a10 read/read a term burst and new read l h l l ba, ca, a10 writ/writ a term burst and new write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall term burst write and precharge* 2 lllh ref, self illegal llllmode mrs illegal write with auto- precharge h desl continue burst to end and precharge lhhh nop continue burst to end and precharge lhhl bst illegal l h l h ba, ca, a10 read/read a illegal* 4 l h l l ba, ca, a10 writ/writ a illegal* 4 l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall illegal* 4 lllh ref, self illegal llllmode mrs illegal refresh (auto- refresh) h desl enter idle after t rc lhhh nop enter idle after t rc lhhl bst enter idle after t rc l h l h ba, ca, a10 read/read a illegal* 5 l h l l ba, ca, a10 writ/writ a illegal* 5 l l h h ba, ra actv illegal* 5 l l h l ba, a10 pre, pall illegal* 5 lllh ref, self illegal llllmode mrs illegal current state s re ce w address command operation
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 32 from idle state, command operation to [desl], [nop], [bst], [pre] or [pall]: these commands result in no operation. to [actv]: the bank specified by the address pins and the row address is activated. to [ref], [self]: the sdram module enters refresh mode (auto-refresh or self-refresh). to [mrs]: the sdram module enters the mode register set cycle. from row active state, command operation to [desl], [nop] or [bst]: these commands result in no operation. to [read], [read a]: a read operation starts. (however, an interval of t rcd is required.) to [writ], [writ a]: a write operation starts. (however, an interval of t rcd is required.) to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) at- tempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands set the sdram module to precharge mode. (however, an interval of t ras is required.) from read state, command operation to [desl], [nop]: these commands continue read operations until the burst operation is completed. to [bst]: this command stops a full-page burst. to [read], [read a]: data output by the previous read command continues to be output. after ce la- tency, the data output resulting from the next command will start. to [writ], [writ a]: these commands stop a burst read, and start a write cycle. to [actv]: this command makes other banks bank active. (however, an interval of t rrd is required.) at- tempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands stop a burst read, and the sdram module enters precharge mode. from read with auto-precharge state, command operation to [desl], [nop]: these commands continue read operations until the burst operation is completed, and the sdram module then enters precharge mode. to [actv]: this command makes other banks bank active. (however, an interval of t rrd is required.) at- tempting to make the currently active bank active results in an illegal command. from write state, command operation to [desl], [nop]: these commands continue write operations until the burst operation is completed. to [bst]: this command stops a full-page burst. to [read], [read a]: these commands stop a burst and start a read cycle. to [writ], [writ a]: these commands stop a burst and start the next write cycle.
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 33 to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) at- tempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands stop burst write and the sdram module then enters precharge mode. from write with auto-precharge state, command operation to [desl], [nop]: these commands continue write operations until the burst is completed, and the sdram module enters precharge mode. to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) at- tempting to make the currently active bank active results in an illegal command. from refresh state, command operation to [desl], [nop], [bst]: after an auto-refresh cycle (after t rc ), the sdram module automatically enters the idle state.
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 34 simplified state diagram mode register configuration the mode register is set by the input to the address pins (a0 to a13) during mode register set cycles. the mode register consists of five sections, each of which is assigned to address pins. a13, a12, a11, a10, a9 a8: (opcode): the sdram module has two types of write modes. one is the burst write mode, and the other is the single write mode. these bits specify write mode. precharge write suspend read suspend row active idle idle power down auto refresh self refresh mode register set power on writea writea suspend reada reada suspend active clock suspend sr entry sr exit mrs refresh cke cke_ active write read write with ap read with ap power applied cke cke_ cke cke_ cke cke_ cke cke_ cke cke_ precharge ap read write write with ap read with read with ap write with ap precharge precharge precharge bst (on full page) bst (on full page) *1 read read write write automatic transition after completion of command. transition resulting from command input. note: 1. after the auto-refresh operation, precharge operation is performed automatically and enter the idle state.
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 35 burst read and burst write: burst write is performed for the specified burst length starting from the column address specified in the write cycle. burst read and single write: data is only written to the column address specified during the write cycle, regardless of the burst length. a7: keep this bit low at the mode register set cycle. if this pin is high, the vender test mode is set. a6, a5, a4: (lmode): these pins specify the ce latency. a3: (bt): a burst type is specified. when full-page burst is performed, only "sequential" can be selected. a2, a1, a0: (bl): these pins specify the burst length. a2 a1 a0 burst length 00 0 1 00 1 2 01 0 4 01 1 8 1 1 1 f.p. bt=0 bt=1 10 0 r 11 0 r 1 2 4 8 r r r a3 0 sequential 1 interleave burst type a6 a5 a4 cas latency 00 0 r 00 1 r 01 0 2* 01 1 3 1xx r a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 opcode 0 lmode bt bl a9 0 0r write mode a8 0 1 burst read and burst write 1 burst read and single write 0 1r 1 10 1 r r f.p. = full page r is reserved (inhibit) x: 0 or 1 note: only -a6. a11 a10 a10 x x x a11 x x x 00 a12 a13 a13 x x x 0 a12 x x x 0
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 36 burst sequence operation of the sdram module read/write operations bank active: before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (actv) command. bank 0, bank 1, bank 2 or bank 3 is activated according to the status of the bank select address (ba) pin, and the row address (ax0 to ax11) is activated by the a0 to a11 pins at the bank active command cycle. an interval of t rcd is required between the bank active com- mand input and the following read/write command input. read operation: a read operation starts when a read command is input. output buffer becomes low-z in the (ce latency - 1) cycle after read command set. the sdram module can perform a burst read operation. the burst length can be set to 1, 2, 4, 8 or full-page. the start address for a burst read is specified by the column address and the bank select address (ba) at the read command set cycle. in a read operation, data output starts after the number of clocks specified by the ce latency. the ce latency can be set to 2 or 3. when the burst length is 1, 2, 4 or 8, the dout buffer automatically becomes high-z at the next clock after the successive burst-length data has been output. the ce latency and burst length must be specified at the mode register. a2 a1 a0 addressing(decimal) 00 0 00 1 01 0 01 1 11 1 interleave sequential 10 0 11 0 10 1 starting ad. 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 2, 3, 4, 5, 6, 7, 3, 4, 5, 6, 7, 4, 5, 6, 7, 5, 6, 7, 6, 7, 7, 0, 0, 1, 0, 1, 2, 0, 1, 2, 3, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 2, 3, 0, 1, 6, 7, 3, 2, 1, 0, 7, 4, 5, 6, 7, 5, 4, 7, 6, 7, 7, 6, 4, 5, 6, 5, 4, 0, 1, 2, 3, 6, 1, 0, 3, 2, 4, 5, 2, 3, 0, 1, 6, 5, 4, 3, 2, 1, 0, burst length = 8 a1 a0 addressing(decimal) 00 01 10 11 interleave sequential starting ad. 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, burst length = 4 a0 addressing(decimal) 0 1 interleave sequential starting ad. 0, 1, 1, 0, 0, 1, 1, 0, burst length = 2
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 37 ce latency burst length write operation: burst write or single write mode is selected by the opcode (a13, a12, a11, a10, a9, a8) of the mode register. 1. burst write: a burst write operation is enabled by setting opcode (a9, a8) to (0, 0). a burst write starts in the same clock as a write command set. (the latency of data input is 0 clock.) the burst length can be set to 1, 2, 4, 8, and full-page, like burst read operations. the write start address is specified by the column ad- dress and the bank select address (ba) at the write command set cycle. read ck command dout actv row column address cl = 2 cl = 3 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 t rcd cl = ce latency burst length = 4 read ck command dout actv row column out 0 out 6 out 7 out 8 address out 0 out 1 out 4 out 5 out 0 out 1 out 2 out 3 bl = 1 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 6 out 7 out 4 out 5 out 0-1 out 0 out 1 bl = 2 bl = 4 bl = 8 bl = full page t rcd bl : burst length ce latency = 2
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 38 2. single write: a single write operation is enabled by setting opcode (a9, a8) to (1, 0). in a single write operation, data is only written to the column address and the bank select address (ba) specified by the write command set cycle without regard to the burst length setting. (the latency of data input is 0 clock). auto precharge read with auto-precharge: in this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. the command exe- cuted for the same bank after the execution of this command must be the bank active (actv) command. in addition, an interval defined by l apr is required before execution of the next command. ce latency precharge start cycle 3 2 cycle before the final data is output 2 1 cycle before the final data is output writ ck command din actv row column in 0 in 6 in 7 in 8 address in 1 in 4 in 5 in 3 bl = 1 in 6 in 7 in 4 in 5 in 0-1 in 0 in 1 bl = 2 bl = 4 bl = 8 bl = full page t rcd in 0 in 0 in 0 in 0 in 1 in 1 in 1 in 2 in 2 in 2 in 3 in 3 ce latency = 2, 3 writ ck command din actv row column in 0 address t rcd
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 39 burst read (burst length = 4) write with auto-precharge: in this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. the command executed for the same bank after the execution of this command must be the bank active (actv) command. in addition, an interval of l apw is required between the final valid data input and input of next command. burst write (burst length = 4) ck l apr l ras l apr cl=2 command cl=3 command dout dout note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ". actv read a actv out3 out2 out1 out0 l ras actv read a actv out3 out2 out1 out0 ck command din l apw i ras actv writ a in0 in1 in2 in3 actv note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ".
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 40 single write full-page burst stop burst stop command during burst read: the burst stop (bst) command is used to stop data output during a full-page burst. the bst command sets the output buffer to high-z and stops the full-page burst read. the timing from command input to the last data changes depending on the ce latency setting. in addition, the bst command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8. ce latency = 2, burst length = full page ce latency bst to valid data bst to high impedance 21 2 32 3 ck command din l apw i ras actv writ a in actv note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ". l = 1 cycle bsr ck command dout out out out out l = 2 cycle bsh bst out out
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 41 ce latency = 3, burst length = full page burst stop command at burst write: the burst stop command (bst command) is used to stop data input during a full-page burst write. no data is written in the same clock as the bst command, and in subsequent clocks. in addition, the bst command is only valid during full-page burst mode, and is illegal with burst lengths of 1, 2, 4 and 8. and an interval of t dpl is required between last data-in and the next precharge com- mand. burst length = full page command intervals read command to read command interval: 1. same bank, same row address: when another read command is executed at the same row address of the same bank as the preceding read command execution, the second read can be performed after an inter- val of no less than 1 clock. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. l = 2 clocks bsr ck command dout out out out out l = 3 clocks bsh bst out out out t ck command din in dpl in pre/pall bst i = 0 clock bsw
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 42 read to read command interval (same row address in same bank) 2. same bank, different row address: when the row address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. 3. different bank: when the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. read to read command interval (different bank) write command to write command interval: 1. same bank, same row address: when another write command is executed at the same row address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. in the case of burst writes, the second write command has priority. ck command dout out b3 address out b1 out b2 ba actv row column a read read column b out a0 out b0 bank0 active column =a read column =b read column =a dout column =b dout ce latency = 3 burst length = 4 bank 0 ck command dout out b3 address out b1 out b2 ba actv row 0 row 1 actv read column a out a0 out b0 bank0 active bank3 active bank0 read bank3 read read column b bank0 dout bank3 dout ce latency = 3 burst length = 4
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 43 write to write command interval (same row address in same bank) 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. 3. different bank: when the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. in the case of burst write, the second write command has priority. write to write command interval (different bank) read command to write command interval: 1. same bank, same row address: when the write command is executed at the same row address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. however, dqmb must be set high so that the output buffer becomes high-z before data input. ck command din in b3 address in b1 in b2 ba actv row column a writ writ column b in a0 in b0 bank0 active column =a write column =b write burst write mode burst length = 4 bank 0 ck command din in b3 address in b1 in b2 ba actv row 0 row 1 actv writ column a in a0 in b0 bank0 active bank3 active bank0 write bank3 write writ column b burst write mode burst length = 4
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 44 read to write command interval (1) read to write command interval (2) 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank- active command. 3. different bank: when the bank changes, the write command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. however, dqmb must be set high so that the output buffer becomes high-z before data input. write command to read command interval: 1. same bank, same row address: when the read command is executed at the same row address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. however, in the case of a burst write, data will continue to be written until one cycle before the read command is executed. ck command dout in b2 in b3 read writ in b0 in b1 high-z din cl=2 cl=3 dqmb burst length = 4 burst write ck command dout read writ din cl=2 cl=3 dqmb high-z 2 clock high-z
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 45 write to read command interval (1) write to read command interval (2) 2. same bank, different row address: when the row address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank- active command. 3. different bank: when the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. however, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address). read with auto precharge to read command interval 1. different bank: when some banks are in the active state, the second read command (another bank) is executed. even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid. the internal auto-precharge of one bank starts at the next clock of the second command. read with auto precharge to read command interval (different bank) ck command din writ read in a0 out b1 out b2 out b3 out b0 dout column = a write column = b read column = b dout ce latency dqmb burst write mode ce latency = 2 burst length = 4 bank 0 ck command din writ read in a0 out b1 out b2 out b3 out b0 dout column = a write column = b read column = b dout ce latency in a1 dqmb burst write mode ce latency = 2 burst length = 4 bank 0
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 46 2. same bank: the consecutive read command (the same bank) is illegal. write with auto precharge to write command interval 1. different bank: when some banks are in the active state, the second write command (another bank) is executed. in the case of burst writes, the second write command has priority. the internal auto-precharge of one bank starts at the next clock of the second command . write with auto precharge to write command interval (different bank) 2. same bank: the consecutive write command (the same bank) is illegal. read with auto precharge to write command interval different bank: when some banks are in the active state, the second write command (another bank) is exe- cuted. however, dqmb must be set high so that the output buffer becomes high-z before data input. the internal auto-precharge of one bank starts at the next clock of the second command. read with auto precharge to write command interval (different bank) ck command ba dout read a read out a0 out a1 out b0 out b1 ce latency = 3 burst length = 4 bank0 read a bank3 read note: internal auto-precharge starts at the timing indicated by " ". ck command ba din writ a writ in b1 in b2 in b3 in a0 in a1 in b0 burst length = 4 bank0 write a bank3 write note: internal auto-precharge starts at the timing indicated by " ".
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 47 2. same bank: the consecutive write command from read with auto precharge (the same bank) is illegal. it is necessary to separate the two commands with a bank active command. write with auto precharge to read command interval 1. different bank: when some banks are in the active state, the second read command (another bank) is executed. however, in case of a burst write, data will continue to be written until one clock before the read command is executed. the internal auto-precharge of one bank starts at the next clock of the second com- mand. write with auto precharge to read command interval (different bank) 2. same bank: the consecutive read command from write with auto precharge (the same bank) is illegal. it is necessary to separate the two commands with a bank active command. read command to precharge command interval (same bank): ck command ba dout din cl = 2 cl = 3 read a writ in b0 in b1 in b2 in b3 burst length = 4 bank0 read a bank3 write note: internal auto-precharge starts at the timing indicated by " ". dqmb high-z ck command ba dout din writ a read out b0 out b1 out b2 out b3 ce latency = 3 burst length = 4 bank0 write a bank3 read note: internal auto-precharge starts at the timing indicated by " ". dqmb in a0
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 48 when the precharge command is executed for the same bank as the read command that preceded it, the min- imum interval between the two commands is one clock. however, since the output buffer then becomes high-z after the clocks defined by l hzp , there is a case of interruption to burst read data output will be inter- rupted, if the precharge command is input during burst read. to read all data by burst read, the clocks defined by l ep must be assured as an interval from the final data output to precharge command execution. read to precharge command interval (same bank): to output all data ce latency = 2, burst length = 4 ce latency = 3, burst length = 4 read to precharge command interval (same bank): to stop output data ce latency = 2, burst length = 1, 2, 4, 8, full page burst ck command dout read pre/pall out a0 out a1 out a2 out a3 cl=2 l = -1 cycle ep ck command dout read pre/pall out a0 out a1 out a2 out a3 cl=3 l = -2 cycle ep ck command dout read pre/pall out a0 high-z l hzp = 2
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 49 ce latency = 3, burst length = 1, 2, 4, 8, full page burst write command to precharge command interval (same bank): when the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. however, if the burst write operation is unfinished, the input data must be masked by means of dqmb for assurance of the clock defined by t dpl . write to precharge command interval (same bank): burst length = 4 (to stop write operation) ck command dout read pre/pall out a0 high-z l hzp = 3 ck command din writ pre/pall t dpl dqmb ck in a0 in a1 command din writ pre/pall dqmb t dpl
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 50 burst length = 4 (to write all data) bank active command interval: 1. same bank: the interval between the two bank-active commands must be no less than t rc . bank active to bank active for same bank 2. in the case of different bank-active commands: the interval between the two bank-active commands must be no less than t rrd . ck in a0 in a1 in a2 command din writ pre/pall in a3 dqmb t dpl ck command address ba bank 0 active actv row actv row bank 0 active t rc
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 51 bank active to bank active for different bank mode register set to bank-active command interval: the interval between setting the mode register and executing a bank-active command must be no less than l rsa . dqmb control the dqmb mask the dq data. the timing of dqmb is different during reading and writing. reading: when data is read, the output buffer can be controlled by dqmb. by setting dqmb to low, the output buffer becomes low-z, enabling data output. by setting dqmb to high, the output buffer becomes high-z, and the corresponding data is not output. however, internal reading operations continue. the laten- cy of dqmb during reading is 2 clocks. writing: input data can be masked by dqmb. by setting dqmb to low, data can be written. in addition, when dqmb is set to high, the corresponding data is not written, and the previous data is held. the latency of dqmb during writing is 0 clock. ck command address ba bank 0 active bank 3 active actv row:0 actv row:1 t rrd ck command address mode register set bank active mrs actv i rsa bs & row code
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 52 reading writing refresh auto-refresh: all the banks must be precharged before executing an auto-refresh command. since the auto- refresh command updates the internal counter every time it is executed and determines the banks and the row addresses to be refreshed, external address specification is not required. the refresh cycle is 4096 cy- cles/64 ms. (4096 cycles are required to refresh all the row addresses.) the output buffer becomes high- z after auto-refresh start. in addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. self-refresh: after executing a self-refresh command, the self-refresh operation continues while cke is held low. during self-refresh operation, all row addresses are refreshed by the internal refresh timer. a self- refresh is terminated by a self-refresh exit command. before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within 64 ms period on the condition (1) and (2) below. (1) enter self-refresh mode within 15.6 m s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. (2) start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 m s after ex- iting from self-refresh mode. ck dout out 0 out 1 l = 2 latency out 3 dod dqmb high-z ck din in 0 in 1 l = 0 latency in 3 did dqmb
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 53 others power-down mode: the sdram module enters power-down mode when cke goes low in the idle state. in power down mode, power consumption is suppressed by deactivating the input initial circuit. power down mode continues while cke is held low. in addition, by setting cke to high, the sdram module exits from the power down mode, and command input is enabled from the next clock. in this mode, internal refresh is not performed. clock suspend mode: by driving cke to low during a bank-active or read/write operation, the sdram module enters clock suspend mode. during clock suspend mode, external input signals are ignored and the internal state is maintained. when cke is driven high, the sdram module terminates clock suspend mode, and command input is enabled from the next clock. for details, refer to the "cke truth table". power-up sequence: the sdram module should be gone on the following sequence with power up. the ck, cke, s , dqmb and dq pins keep low till power stabilizes. the ck pin is stabilized within 100 m s after power stabilizes before the following initialization sequence. the cke and dqmb is driven to high between power stabilizes and the initialization sequence. this sdram module has v cc clamp diodes for ck, cke, s , dqmb and dq pins. if these pins go high before power up, the large current flows from these pins to v cc through the diodes. initialization sequence: when 200 m s or more has past after the above power-up sequence, all banks must be precharged using the precharge command (pall). after t rp delay, set 8 or more auto refresh commands (ref). set the mode register set command (mrs) to initialize the mode register. we recommend that by keeping dqmb to high, the output buffer becomes high-z during initialization sequence, to avoid dq bus contention on memory system formed with a number of device. v cc power up sequence initialization sequence 100 s 0 v low low low cke, dqmb ck s , dq 200 s power stabilize
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 54 timing waveforms read cycle bank 0 active bank 0 read bank 0 precharge ck cke s t ras t rcd t ch t cs # # ' / 7 ' / 7 ' / . / 6 7 = > . / 6 7 = >

( 0 1 8 ? ( 0 1 8 ? & ' & ' & ' & - . 4 5 < = & - . 4 5 < = 9 9 $ % + , 3 4 $ % + , 3 4 + 3 : ; 3 : ;

%
% & , - 4 ; < 1 8 9 1 8 9 % & , - 3 4 < % & , - 3 4 < 3 ; < 3 ; < & re ce w a12/a13 * 2 3 : * 2 3 : ! " ( ) 0 1 8 ! " ( ) 0 1 8 ! ( ) 0 8
$ % , - 3 4 : ; b c k l " # 6 = > ' . / 6 7 9 : # $ + 3 # $ + 3 ( / 7 ? > ? > ? ( /0 7 ? " ) * 1 2 1 8 9 a10 address dqmb din dout + 3 ; : ;
t ch t cs t ckh t t ck t ac t ac ckl t ac t oh t oh t oh t oh t rp t rc ce latency = 2 burst length = 4 bank 0 access = v or v $ ( + , 0 3 8 : ; ? 1 8 9 t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ac # $ * + 2 : > ? 9 : t lz v ih ih il + , 3 4 t hz
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 55 write cycle ck cke s t ras t rcd $ + , 3 4 " " # $ +
" #
re ce w a12/a13 a10 address din dout t ch t cs t ckh t t ck t dh t dh ckl t dh t dh t ds t ds t ds t ds t rp t rc t dpl bank 0 write t ch t cs bank 0 active bank 0 precharge t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ah t as t ah t as t ah t as t ch t cs t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ch t cs t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ah t as ! ! " ( ) 0 1 8 ! $ ! ( /0 / 7 > ?
( / & - . 5 6 < = & ' ' /
* 2 9 : $ / 7 > ? $ % + , 3 4 ; 0 8
% & , - 4 5 ; < & 8
: ;

' ( - . . / 6 7 = > $ % 8 ? v ih ce latency = 2 burst length = 4 bank 0 access = v or v ! ih il dqmb
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 56 mode register set cycle read cycle/write cycle m n 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ck cke s re ce w ba address dqmb din dout @ h i & ' / d m n h p & . / 7 & ' / $ % - . - 6 > g f g o p ; c d k l high-z b b+3 b? b?+1 b?+2 b?+3 l valid c: b? rsa code l rcd l rp precharge if needed mode register set bank 3 active bank 3 read h ? @ h i / 7 8 a & . / 7 8 ; d l m ' ( / 0 ( n 6 ? @ h - 6 ? g o p % & - . 7 & r: b c: b . 6 7 ? @ h p 4 5 < = f output mask v ih l = 3 ce latency = 3 burst length = 4 = v or v ih il rcd 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b c:b c:b' c:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 cke re s ce w address dqmb dout din ck ba = f o < = e < = e f f g o = e f r:a c:a r:b c:b c:b' c:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3

h i
i a b j k 8 a j 7 8 @ a a b j 8 @ a j i j @ i i j @ i 9 : b 0 9 b ' 0 8 9 ' / 0 8 9 ' / 0 8 a ( 1 : ' ( 0 1 ' ( 0 ( 0 1 ' ( 0 5 > f g 4 5 = f + 4 5 = 5 = > f 4 5 = > f - 5 > + , 5 , 5 > , 5 > # , 5 $ % - #$ , # , $ - $ , %

( ! ( ) 1 2 ( ) 1 ( 1 ( k l b k l b j k 9 b j k j k k j k 9 a b j bank 0 active bank 0 read bank 3 active bank 3 read bank 3 read bank 3 read bank 0 precharge bank 3 precharge bank 0 active bank 0 write bank 3 active bank 3 write bank 3 write bank 3 write bank 0 precharge bank 3 precharge cke re s ce w address dqmb din dout ba high-z high-z 4 5 = e f $ % / 7 8 ? @ i 1 9 : b c v ih v ih read cycle re - ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il write cycle re - ce delay = 3 ce latency = 3 burst length = 4 = v or v ! ih il
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 57 read/single write cycle n e m n e n e m n f g o p = e f n o = f g n o = e f n 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 $ , # , ! * ! * r:a c:a r:b c:a' # , # , r:a c:a c:a $ - ! a a a a $ $

bank 0 active bank 0 read bank 3 active bank 0 write bank 0 precharge bank 3 precharge bank 0 active bank 0 read bank 0 write bank 0 precharge ) * 2 ) * 2 ) 2 ) < = e n r:b bank 3 active > f g p = > f g = > f 4 = > f + 4 = k l k l b j k 9 b j k $ % - 6 > $ % - 5 > $ ,- 5 > $ , 4 5 > # + , 4 5 8 9 a i j
9 a b i j
9 a b j k
9 b j k
b k l c:a bank 0 read a a+1 a+2 a+3

9 a b j k

% %

bank 0 write bank 0 write cke re s ce w address dqmb din dout ck ba cke re s ce w address dqmb ba ' ( 0 1 9 ( ) 0 1 9 : ) 2 : ; c l ) 1 2 9 : c ( ) 1 2 9 : c:b bc a+1 a+3 a+1 a+2 a+3 c:c ! " * + 2 3 ) ! * ! * 3 > f g o p # + , 3 4 < = ) 1 2 : & v ih v ih read/single write re - ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il din dout
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 58 read/burst write cycle < d e n 2 ; < d < d e ; < d < e n 4 < = e f 3 4 < e 4 < = e * 3 4 < & / 0 7 8 ? @ i / 0 8 @ a i 0 8 9 @ a i j 0 8 9 a b i j & ' & ' 0 ' ( 0 ( ) 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 # r:a c:a r:b c:a' # r:a c:a c:a
j
a i j @ a i # a a+1 a+2 a+3 a+1 a a+1 a+2 a+3 h p

i h i ? h i ? h bank 0 active bank 0 read bank 0 write bank 0 precharge ' ( 0 1 ) & . / 7 8 ? @ * 2 3 < r:b bank 3 active 4 5 = + 4 5 = " + 4 " * + 4 " * + 9 b j k 9 a b j 8 9 a b j / 8 9 @ a / 7 8 @ a h i #$ , 5 # + , 5 " # + , " # + " # + cke re s ce w address dqmb ck ba cke re s ce w address dqmb ba a+1 a+2 a+3 a a+3 a
a i j ' ( 0 1 * 2 3 : ; c d " + 3 4 < & ' bank 0 active bank 0 read bank 3 active clock suspend bank 0 write bank 0 precharge bank 3 precharge & ' . / 6 7 @ " v ih read/burst write re - ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il din dout din dout
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 59 full page read/write cycle auto refresh cycle high-z

z r:a c:a r:b
e o y d e n d e n o o y e n o r:a c:a r:b high-z
\ [ \ q z [ [ \ q [ \ \ ] h r \ h q r r \ h q r \ 2 < f o ; d e o 1 ; d e 2 < e o 2 ;< e o 2 3 < ( 12 ; ( 2 3 < ( 2 < ( 2 ; # # $ # $ . $ % . bank 0 active bank 0 read bank 3 active burst stop bank 3 precharge bank 0 active bank 0 write bank 3 active burst stop bank 3 precharge @ i j s ] ? @ i j r s ? @ h i r s 5 ? @ h i r 5 > ? h i r # , - 5 6 ? @ - 6 7 @ a j # - 6 7 ? @ j # , - 6 7 ? @ $ - . # $ - . # $ - s t ] ^ t ] ^ t ^ ^ ] " # , 5 6 ? * ) * 2 3 ( ) 2 3 ( ) 2 ( ) 2 ( 2 s t \ ] cke re s ce w address dqmb din dout ck ba cke re s ce w address dqmb ba ; d e n o x d m n v w a > h q r v ih v ih a a+1 a+2 a+3 read cycle re - ce delay = 3 ce latency = 3 burst length = full page = v or v ih il write cycle re - ce delay = 3 ce latency = 3 burst length = full page = v or v ih il a a+1 a+2 a+3 a+6 a+5 a+4 din dout 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ck cke s ce w ba address dqmb din dout & ' / 7 8 ? @ h i
i j d m % & / 7 8 ? @ h i high-z rp ! ) 1 2 1 9 : c g p / 8 @ a h i
i & / 0 8 " 6 ? @ h + , 4 5 ' + 4 < = e f m n 6 ? h & ' / precharge if needed auto refresh active bank 0 t rc t rc t auto refresh read bank 0 r:a c:a a10=1 re
! ) * 1 2 ; 1 : ; c h p
8 a i j

# , 4 5 9 < = a b f j k a a+1 v ih refresh cycle and read cycle re - ce delay = 2 ce latency = 2 burst length = 4 = v or v ih il
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 60 self refresh cycle clock suspend mode $ % - . 6 ck cke s re ce w ba address dqmb din dout
$ , 1 2 4 5 : ; = > b c f j k . 6 7 ? @ h . 7 8 ? @ h ) 2 : ; : b c l
: b c j k $ , 5 = > e f n ? h p 6 7 ? h p ' ( 5 = > $ , 5 precharge command if needed self refresh entry command auto refresh self refresh exit ignore command or no operation f g o p ' ( 0 1 7 ? @ h i ( n o ? h p n o cke low ! " ) * 2 7 : ; ? @ c h k l a10=1 rc t rp t # ,
#$ , 4 5 = > e f m n
#$ , 4 5 < = e f m n self refresh cycle re - ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il high-z next clock enable 5 > f g n o 5 = > f n o 4 5 = > e f n rc t next clock enable l srex self refresh entry command < d e m n ' ( / 0 9 l m < d e l m ! * + 3 + 3 4 < = g p 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 & b k " # + 4 ! " ) * 2 3 # + , 4 r:a c:a r:b a a+1 a+2 a+3 b b+1 b+2 ! " + h r:a c:a r:b c:b m gh p h p a a+1 a+2 b b+1 b+2 b+3 & " # + h m c:b b c k l bank0 active active clock suspend start active clock supend end bank0 read bank3 active read suspend start read suspend end bank0 precharge bank3 read earliest bank3 precharge bank0 write bank0 active active clock suspend start active clock suspend end bank3 active write suspend start write suspend end bank3 write bank0 precharge earliest bank3 precharge c l l c k l b+3 + 3 4 < * + 3 < k ; < d l m 2 ; < c d l 2 : ; c d l ) 2 : ; b c l . 7 8 ? @ h % - . 6 7 ? g % . 6 7 ? h 7 8 @ h i ' / 0 8 & ' / 8 % & / . 6 7 ? @ h & ' / % & cke re s ce w address dqmb ck ba cke re s ce w address dqmb ba a+3 high-z high-z " # + , 4 5 = > ! ( ) 1 2 9 : a b k & . / 6 7 @ t ces t ceh t ces read cycle re - ce delay = 2 ce latency = 2 burst length = 4 = v or v ih il write cycle re - ce delay = 2 ce latency = 2 burst length = 4 = v or v ih il 7 8 @ h i dout din dout din
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 61 power down mode initialization sequence ck cke s re ce w ba address dqmb din dout
$ , 4 5 = > e f n o & ' / 0 8 & ' / ! " . / 6 7 ? @ h p ! " + % - . 6 >? g o p ! % & $ % - 56 = > f g n o % precharge command if needed power down entry active bank 0 power down mode exit
8 a i j ' ( / 0 8 9 / 8 9 @ a h i j " # + / 7 8 ? @ h / 7 8 ? @ h i / 7 8 ? @ h i cke low r: a a10=1 rp t # high-z power down cycle re - ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il 78910 52 53 54 48 49 50 51 ! ( ) 1 2 : g o p auto refresh bank active if needed rc t rc t auto refresh valid c k l 0 123456 ck cke s re ce w address dqmb dq 8 9 a b j
a i j 7 @ a h i . 7 ? @ h t valid rsa t rp all banks precharge mode register set @ a i / 8 9 a v ih v ih ! * ! ! ) 55 high-z ' ( / 0 8 9 a 3 4 ; < d e m 4 < = d e m n / 7 8 a ) b c k 9 b c k 6 ? g p code
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 62 physical outline cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copy- right, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have re- ceived the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, con- tact hitachis sales office before using the product in an application that demands especially high quality 6.35 0.250 6.35 0.250 1.00 0.039 detail b detail c detail a 0.20 0.15 2.50 0.20 0.010 0.0004 0.098 0.008 3.125 0.125 3.125 0.125 0.123 0.005 0.123 0.005 1.27 0.050 3.00 typ 133.37 0.15 0.118 typ 5.251 0.006 3.00 0.10 0.118 0.004 11.43 36.83 54.61 0.450 2.150 (63.67) (2.51) 1.450 a b c 1 84 front side back side 85 4.00 0.10 0.157 0.004 17.80 0.70 34.925 1.375 168 2 e f 3.00 0.10 2 e f 0.118 0.003 1.00 0.05 0.039 0.002 2.00 0.10 0.079 0.004 4.175 0.164 2.00 0.10 0.079 0.004 (datum -a-) (datum -a-) unit: mm inch (datum -a-) r full r full note: tolerance on all dimensions 0.15/0.006 unless otherwise specified. 127.35 0.15 5.014 0.006 component area (front) component area (back) 1.27 0.10 4.00 min 0.157 min 0.050 0.004 4.00 max 0.157 max
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 63 and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or fail- ure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equip- ment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor prod- ucts. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan . hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:
HB52E88EM-f, hb52e89em-f, hb52e168en-f, hb52e169en-f 64 revision record rev. date contents of modification drawn by approved by 0.0 apr. 16, 1999 initial issue (referred to hm5264165f/hm5264805f/hm5264405f- 75/a60/b60 rev 0.1)

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